Shielded microelectronic connector assembly and method of manufacturing
US6585540B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2000 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Dec 6, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S439/941
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An advanced multi-connector electronic assembly incorporating different noise shield elements which reduce noise interference and increase performance. In one embodiment, the connector assembly comprises a plurality of connectors with associated electronic components arranged in two parallel rows, one disposed atop the other. The assembly utilizes a substrate shield which mitigates noise transmission through the bottom surface of the assembly, as well as an external “wrap-around shield to mitigate noise transmission through the remaining external surfaces. In a second embodiment, the connector assembly further includes a top-to-bottom shield interposed between the top and bottom rows of connectors to reduce noise transmission between the rows of connectors, and a plurality of front-to-back shield elements disposed between the electronic components of respective top and bottom row connectors to limit transmission between the electronic components. A method of manufacturing the assembly is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.