Reducing copper line resistivity by smoothing trench and via sidewalls
US6586334B2 · kind B2 · utility
18Cited by
5References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 11, 2001 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Oct 11, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76835
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an integrated circuit. A thin liner (110, 210, 310) is deposited over dielectric layer including within a trench (108) and/or via (106). The thin liner (110, 210, 310) smoothes the sidewalls of the trench (108) and/or via (106) and reduces resistivity. The thin liner may comprise an organic or inorganic dielectric (110) or metal (210,310). A copper interconnect structure (116, 216, 316) is then formed over the thin liner (110, 210, 310).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.