Method and structure for a single-sided non-self-aligned transistor
US6586806B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 1997 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Sep 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor includes a non-self-aligned gate-terminal junction in a substrate having a relatively thick oxide layer disposed between a gate region and a terminal region and a relatively thin oxide layer disposed between the gate structure and the substrate. The terminal region may be the drain region of the transistor and it may include a buried N+ region within the substrate. The transistor may be formed in a p-well. Further, the transistor may also include a self-aligned gate-terminal junction between the gate structure and a source region. In a further embodiment, a transistor fabrication method includes forming an active area in a substrate and implanting an N-type impurity into a first terminal region of the active area. An oxide layer is differentially grown over the active area so that the oxide layer has a first thickness over the first terminal region and a second thickness over the remaining portion of the active area. The first thickness is substantially thicker than the second thickness and, in some embodiments, may be up to twice as thick as the second thickness. A gate structure is formed within the active area, overlapping the oxide layer over the first terminal reg…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.