Integrated circuit devices having power control logic that inhibits internal leakage current loss during sleep mode operation and method of operating same
US6586963B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2002 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Jan 3, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0036
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Integrated circuit devices utilizes on-chip power down control circuitry to control the timing of application of at least one external power signal to the device when a functional logic circuit within the device is switching in and out of an inactive mode of operation, such as a sleep mode. During a respective inactive mode, the leakage current characteristics of the respective functional logic circuit are improved by removal of the external power signal. The at least one external power signal may be provided by one or more power transistors operating in response to signals generated by external power transistor control circuitry. These power transistors may provide power to respective power supply pins that are coupled on-chip to the device and the external power transistor control circuitry may be responsive to one or more signals generated by the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.