Programmable bit ordering for serial port
US6586968B1 · kind B1 · utility
15Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2001 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Dec 19, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4291
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An order in which bits for serial data are transmitted or received by a first device, integrated circuit (IC) or logic, is programmable to be either from most significant bit (MSB) to least significant bit (LSB) or from LSB to MSB. Therefore, when the first device is used with a second device, integrated circuit (IC) or logic, which can handle the serial data in only one order, the first device is programmed, or configured, to handle the serial data in the same order as the second device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.