Adapting VLSI clocking to short term voltage transients
US6586971B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2001 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Dec 18, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/305
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of compensating for voltage droop in an integrated circuit. The integrated circuit may include a plurality of chip circuits, a clock control system, a clock distribution network including at least one delay element and a voltage droop detector. The clock control system adapts cycle time in the clock distribution network through use of the at least one delay element when a voltage droop is detected. The method may include detecting a voltage droop in an integrated circuit where the integrated circuit is driven by a clock signal, determining an optimum frequency change to compensate for the voltage droop, and adapting cycle time of the clock signal in an incremental manner to achieve the optimum frequency change.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.