Circuit with source follower output stage and adaptive current mirror bias
US6586987B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 14, 2001 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Jun 14, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/267
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A source follower output stage achieves low output impedance and high power supply rejection while operating at low output voltage and low supply voltage. This circuit has improved performance due to the source follower transistor, the sense transistor, and the output mirror, these items forming a common source difference amplifier. This common source difference amplifier adjusts the common voltage of the signal mirror to equalize the signal mirror input and output voltage. Thus, the common node of the mirror adapts to changing supply voltage, output load current and temperature so that the effect on source follower output voltage is minimized. Since the output node of the signal mirror is clamped to the source follower output instead of the common node of the mirror, the circuit operates at lower output and supply voltage than the prior art. For optimum performance, the current density ratio of the output mirror devices is equal to the current density ratio of the sense transistor to the source follower transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.