Correlated double sampler with single amplifier
US6587143B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 19, 1999 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Jan 19, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/75
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A correlated double sampler (CDS) circuit having a ping/pong architecture which employs only a single amplifier, and a CCD image sensor output processing circuit including such a CDS circuit and preferably also an analog-to-digital converter for processing the output of the CDS circuit and a black level correction feedback loop. In one cycle of operation (during processing of the raw output of a CCD sensor), the CDS circuit receives a first set of control signals followed by a second set of control signals, its output signal in response to the first set is indicative of the value of one pixel of a sensed image, and its output signal in response to the second set is indicative of the value of the next pixel of the image. Preferably, each set of control signals consists of a clamp signal, a sample signal, and a hold signal. Since the output signal of the CDS circuit has the same offset voltage for all pixels of an image, black level correction can be implemented using only one black level correction feedback loop. Use of a single amplifier (rather than two) and one black level correction loop (rather than two) reduces power consumption. Preferably, the amplifier of the CDS circuit pr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.