Method and apparatus for reducing on-chip memory in vertical video processing
US6587158B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 1999 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Jul 22, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/426
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A digital image processor includes an input buffer for storing raster-scanned data. A slice-buffer memory is coupled to the input buffer to store a portion of a vertical slice of said raster-scanned data. The vertical slice is processed by a vertical slice processor having an input coupled to the slice-buffer memory. The vertical slice processor reassembles the vertical slices into processed raster-scanned data in an output buffer that is coupled to the output of the vertical slice processor. The digital image processor preferably utilizes multiple sequential processing stages and processes the raster-scanned data along the horizontal axis of the vertical slices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.