System and method for increasing performance in a compilable read-only memory (ROM)
US6587364B1 · kind B1 · utility
6Cited by
3References
21Claims
0Family size
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Key dates
| Filing date | Apr 23, 2002 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Apr 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compilable ROM architecture with enhanced performance characteristics, i.e., increased speed and lowered power consumption, wherein a plurality of memory locations are organized into one or more I/O blocks, each having a select number of bitlines. Each memory location is addressable by a row address and a column address. The data is stored in the ROM using a scrambled addressing scheme wherein a portion of the row and column addresses is interchanged in order to minimize bitline loading of the binary 0's.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.