Packet classification engine
US6587463B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 1999 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Dec 13, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/43
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Packet classification apparatus includes a rule memory and a criterion memory. One type of rule memory entry contains an operator and a pointer to a criterion memory entry. The operator defines a comparison operation to be performed, such as EQUAL (exact match) or LESS THAN. The criterion memory entry contains one or more values to be used as comparands on one side of the comparison, where corresponding values from a received packet appear on the other side of the comparison. Control logic responds to packet classification requests to retrieve a rule memory entry from the rule memory, retrieve the criterion memory entry identified by the criterion memory pointer in the rule memory entry, and perform the operation specified by the operator in the rule memory entry on the values in the criterion memory entry and corresponding values included in the classification request. This procedure is repeated for a sequence of rule memory entries until an ending condition is encountered, whereupon a packet classification result is generated reflecting the result of the classification operations. This result is provided to a packet processor to take the appropriate action based on the classifica…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.