Clock recovery circuit and a receiver having a clock recovery circuit
US6587531B1 · kind B1 · utility
3Cited by
7References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 18, 1999 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Feb 18, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/07
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data receiver comprises a receiver for receiving a data signal and providing a base band output, a demodulator coupled to an output of the receiving means receiver for providing a data output, and a clock recovery circuit coupled to an output of the demodulator for recovering symbols represented by the data output. The clock recovery circuit is operable to determine a time difference between rising and falling edges in the data output and their nominal reference points, and to determine respective clock reference points for the rising and falling edges from the time difference between the rising and falling edges.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.