Method and system for computing 8×8 DCT/IDCT and a VLSI implementation
US6587590B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 22, 2000 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Feb 22, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for computing 2-D DCT/IDCT which is easy to implement with VLSI technology to achieve high throughput to meet the requirements of high definition video processing in real time is described. A direct 2-D matrix factorization approach is utilized to compute the 2-D DCT/IDCT. The 8×8 DCT/IDCT is computed through four 4×4 matrix multiplication sub-blocks. Each sub-block is half the size of the original 8×8 size and therefore requires a much lower number of multiplications. Additionally, each sub-block can be implemented independently with localized interconnection so that parallelism can be exploited and a much higher DCT/IDCT throughput can be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.