System and method for delay line testing
US6587811B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2001 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Oct 3, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/133
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A circuit generates a test signal useful in verifying the actual delay values of individual delay stages in a digital delay line. In general, the cumulative delay of the delay line defines a window in time having its zero point anchored to the beginning of the delay line. Successive delay stages correspond to successive time bins within the overall time window. The test signal shifts at a known, linear rate in time with respect to a reference signal, which is used to initiate a test cycle. The reference signal synchronizes sampling of the test signal to the beginning of the time window. Samples of the test signal are taken at sample points determined by the actual time delays in the successive delay stages. The observed distribution of test signal edges across the time window may be used to determine the actual delay intervals of the delay line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.