PCI bus system testing and verification apparatus and method
US6587813B1 · kind B1 · utility
28Cited by
2References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2000 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Apr 11, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4269
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved PCI verification method and apparatus provides iterative testing of all desired conditions or protocol combinations in a PCI system. One or more commands may be tested in combination with one or more functional behavior parameters throughout a desired range of variable parameter values. In one aspect, an apparatus and method for testing a PCI device for compliance under the PCI specification in target operation is provided. In another aspect, an apparatus and method for testing a PCI device for compliance under the PCI specification in master operation is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.