Method and apparatus for preventing loops in a full-duplex bus
US6587904B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 1999 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Nov 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/50
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is disclosed for preventing loops in a full-duplex bus. One method has the acts of: selecting at least two candidates to join said bus; establishing a dominant candidate from one of said at least two candidates; testing for loops in said bus; and joining said dominant candidate if no loops are found in said bus. Another method has the acts of: selecting a plurality candidates to join said bus; establishing at least one dominant candidate; testing for loops in said bus; and joining said at least one dominant candidate if no loops are found in said bus. Alternative embodiments are shown that utilize unique identifiers to facilitate candidate selection and to establish dominance on the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.