Memory architecture for supporting concurrent access of different types
US6587917B2 · kind B2 · utility
37Cited by
7References
14Claims
0Family size
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Key dates
| Filing date | May 29, 2001 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Jun 30, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory architecture for supporting mixed-mode memory accesses. A common row address is provided. A first column address for accessing a first column and a second column address for accessing a second column are provided. A first write control signal for specifying one of a write access and a read access for the first column, and a second write control signal for specifying one of a write access and a read access for the second column are also provided. The memory architecture, responsive to these input signals, supports concurrent mixed-mode memory accesses to the first column and a write access to the second column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.