Dual line size cache directory
US6587923B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 22, 2000 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | May 22, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer system having a processor, a memory system including multiple levels of caches L1, L2, . . . , Ln−1 and including main memory Ln, and in which the cache Li−1 includes lines of size s and the cache Li includes lines of size t with t>s, a dual line size cache directory mechanism, in which the contents of a cache Li−1 may be accessed at line size granularity s (in which case it is determined whether a line corresponding to a given memory address is stored in Li−1, and if so its location and status), and in which the contents of Li−1 may also be accessed at line size granularity t (in which case it is determined whether any of the t/s lines of size s residing in the larger line of size t corresponding to a given memory address are stored in Li−1, and if so their locations and status) without multiple sequential accesses to a cache Li−1 directory structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.