System and method for verification of off-chip processor code
US6587947B1 · kind B1 · utility
30Cited by
15References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 1, 1999 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Apr 1, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/64
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic system and corresponding method for verifying the integrity of code that is stored off-chip. The electronic system comprises a memory element to store Processor Abstraction Layer (PAL) code and a processor coupled to the memory element. The processor verifies the integrity of the PAL code prior to execution of the PAL code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.