Two dimensional compaction system and method
US6587992B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 20, 2002 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | Jun 20, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to layouts with geometrical objects, and more particularly, to a system and method for compacting layouts in two dimensions simultaneously. In an embodiment, the system and method of the present invention are applied to IC layouts. The present invention provides for compacting layouts in two dimensions at once without depending on expensive methods such as Branch and Bound. As a result, in an embodiment, the present invention can be applied to large layouts in much the same way as conventional, one dimensional compaction systems and methods. The present invention also provides for compacting hierarchical layouts in two dimensions at once while preserving the complete hierarchy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.