Modeling delays for small nets in an integrated circuit design
US6587999B1 · kind B1 · utility
9Cited by
10References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 15, 2001 |
| Grant date | Jul 1, 2003 |
| Priority date | — |
| Expiry date | May 15, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of modeling delays in an integrated circuit design is disclosed that may be used to reduce the computation time of path delays in an integrated circuit design. A method of modeling delays in an integrated circuit design includes the steps of receiving as input a description of an integrated circuit design; identifying at least one small net in the integrated circuit design from the description; approximating an effective capacitance of the at least one small net by the total capacitance; and approximating an interconnect delay of the at least one small net by zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.