Inter-layer connection structure, multilayer printed circuit board and production processes therefor
US6589870B1 · kind B1 · utility
46Cited by
8References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 4, 2000 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Feb 4, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1476
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A process for forming a bump via to interconnect upper and lower circuits wherein a layer of metal is etched down, leaving a bump via and a lower portion of the layer. A lower circuit pattern is then formed in the lower portion, following which the pattern and bump via are covered with an insulating layer. Smoothing then results in the top surface of the bump via being exposed such that an upper circuit can then be formed on the insulating layer and in connection with said bump via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.