Video bus for high speed multi-resolution imagers
US6590198B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2000 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Jan 24, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/78
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An analog video bus architecture that utilizes the column parallel nature of CMOS imagers and more specifically Active Column Sensors, that eliminates the need for multi-port imagers, by increasing the useable bandwidth of single port imagers. An adaptation of this invention allows for either binning or interpolation of pixel information for increased or decreased resolution along the columns and more specifically for ACS imagers binning or interpolation along the rows. In this bus, the single video bus is replaced by multiple video buses and instead of selecting only one column for reading multiple columns are also pre-selected in-order to pre-charge the video bus. The video buses are then de-multiplexed back on to one port at the desired element rate. This architecture utilizes the column oriented video bus of CMOS imagers. It divides the large video bus capacitance by the number of video buses used. In addition, it allows multiple pixel time constants to precharge the video bus. The best commercially available imager designs now claim 40 MHz per analog port and suffer from reduced signal to noise ratios. To overcome this fundamental bandwidth limitation, imager designs in the pa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.