Thin film transistor array substrate, method for manufacturing the same and system for inspecting the substrate
US6590226B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2001 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Oct 5, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136254
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Disclosed is a thin film transistor substrate and a system for inspecting the same. The thin film transistor substrate comprises gate wiring formed on an insulation substrate and including gate lines, and gate electrodes and gate pads connected to the gate lines; a gate insulation layer covering the gate wiring; a semiconductor layer formed over the gate insulation layer; data wiring formed over the gate insulation layer and including data pads; a protection layer covering the data wiring; auxiliary pads connected to the data pads through contact holes formed in the protection layer; and a pad auxiliary layer formed protruding a predetermined height under the data pads. The inspection system for determining whether a thin film transistor substrate is defective, in which the thin film transistor substrate comprises gate wiring including gate lines, gate electrodes and gate pads, and data wiring including source electrodes and drain electrodes, includes a probe pin for contacting the gate pads or data pads and transmitting a corresponding signal, wherein a contact tip at a distal end of the probe pin for contacting the gate pads or the data pads is rounded, and a radius of the rounde…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.