MOS transistors with improved gate dielectrics
US6590241B1 · kind B1 · utility
1Cited by
2References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 7, 2000 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Mar 7, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The specification describes silicon MOS devices with gate dielectrics having the composition Ta1−xAlxOy, where x is 0.03-0.7 and y is 1.5-3, Ta1−xSixOy, where x is 0.05-0.15, and y is 1.5-3, and Ta1−x−zAlxSizOy, where 0.7>x+z>0.05, z<0.15 and y is 1.5-3. By comparison with the standard SiO2 gate dielectric material, these materials provide improved dielectric properties and also remain essentially amorphous to high temperatures. This retards formation of SiO2 interfacial layers which otherwise dominate the gate dielectric properties and reduce the overall effectiveness of using a high dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.