Semiconductor device and manufacturing method therefor
US6590291B2 · kind B2 · utility
106Cited by
9References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 25, 2001 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Jan 25, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15331
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor chips having a thickness of 50 &mgr;m or so are imbedded and mounted inside a package, such that multi-level stacking is facilitated by providing external connection terminals on both surfaces of the package, or, alternatively, exposing the terminal formation portions of the wiring pattern, to which the external connection terminals are to be connected, out of a solder resist layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.