Heterogeneous interconnection architecture for programmable logic devices
US6590419B1 · kind B1 · utility
27Cited by
22References
22Claims
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Key dates
| Filing date | Oct 12, 1999 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Oct 12, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17704
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interconnection architecture for programmable logic devices (PLDs) is presented in which heterogeneous interconnect resources can be programmably connected to function blocks in accordance with two or more operational parameters, such as, for example, signal propagation speed, circuit area, signal routing flexibility, and PLD reliability. Programmable interconnect resources include unbalanced multiplexers, different types of interface buffers, and signal wires of different widths and different wire-to-wire spacings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.