Phase frequency detector circuit having reduced dead band
US6590427B2 · kind B2 · utility
15Cited by
30References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2001 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Sep 4, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital phase detector that conducts pump up and pump down control signals to a charge pump, wherein each of the control signals has pulses that have a substantially 50/50 duty cycle characteristic when the two input signals, i.e., the input data signal and the feedback clock signal, are substantially in phase. This substantially 50/50 duty cycle output reduces, if not eliminates, inherent problems related to the turn-on delays of the charge pump while maintaining a locked condition. The phase detector may further include an intelligence to detect and handle other situations, such as missing data pulses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.