Dynamic biasing for cascoded transistors to double operating supply voltage
US6590443B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 13, 2002 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | May 13, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/242
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
Cascoded transistors can be used to allow circuits to operate at higher operating voltages than the voltages at which individual transistors (formed by a given process) can function. However, common techniques for cascading transistors result in circuits being unable to operate at lower operating voltages. The present invention dynamically biases cascoded transistors in response to the level of the operating voltage, which can vary. Providing separate dynamic bias voltages for N-type and P-type CMOS devices allows circuits using this technique to achieve a wider operating voltage. The wider operating range makes circuits using this technique readily adaptable to a range of power supplies (e.g., different battery configurations) and applications (e.g., driving displays).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.