Clock generator circuit with a PLL having an output frequency cycled in a range to reduce unwanted radiation

US6590458B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Gerd Rombach · Freising, DE
• Hermann Seibold · Alzenau, DE

Key dates

• Filing date: Oct 3, 2001
• Grant date: Jul 8, 2003
• Expiry date: Oct 3, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03L7/18
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A clock generator including a PLL circuit serves to generate an output frequency cycled in a predefined range and containing a desired clock frequency. The PLL circuit contains a voltage-controlled oscillator (18), the oscillating frequency of which is adjustable by means of an analog control voltage to the desired clock frequency in a fixed relationship to a reference frequency applied to the PLL circuit. The clock generator contains a second voltage-controlled oscillator (22), the oscillating frequency of which can be cycled in the predefined range. The second oscillator (22) is configured so that its oscillating frequency can be varied by means of a digital incrementally variable control signal in the predefined range. By varying the output frequency of the clock generator a spreading of its output frequency spectrum is attainable, resulting in a reduction in high-frequency interference by the signal generated by the clock.