Apparatus and method for an improved subranging ADC architecture using ladder-flip bussing
US6590518B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 3, 2001 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Apr 3, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/365
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronic circuit that converts an analog input to a digital signal includes a series “string” of resistors that provides reference signals with ascending values across the string. The reference signals are organized in banks of reference signals, with each adjacent set sharing a major code boundary. A coarse bank of comparators compare the analog input to the major code boundary reference signals and provide a coarse logic output. Each bank of reference signals has a corresponding bank of switches, with each switch associated with a particular reference signal in the bank. All of the switches in a particular bank are closed or opened in unison when selected. A particular bank is selected based on the coarse logic output signal. The reference values corresponding to the selected bank are coupled to a fine bank of comparators, each fine bank comparator comparing the analog input signal to one of the selected reference values. The fine bank of comparators output a fine logic output that corresponds to one of a thermometer code and a reverse thermometer code. The switches that couple the reference values to the fine bank of comparators are arranged in a “ladder-f…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.