Method of reducing errors in displays using double-line sub-field addressing
US6590571B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2001 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Oct 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0205
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Method of calculating new luminance value data based on original luminance value data to be displayed on a matrix display device, where luminance value data are coded in sub-fields, and double-line addressing for the least significant sub-fields is used for reducing the addressing time. A reduction of the difference between the new data and the original data is obtained by computing a new common value for the least significant sub-fields of a set of neighboring or adjacent lines, and new values for the most significant sub-fields of each line of said set of adjacent lines. The method comprises embodiments which are applicable to both binary and non-binary sub-fields.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.