Method and apparatus for detecting and suppressing a parallel arc fault
US6590757B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2001 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Dec 4, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H1/0015
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Electrical equipment (14) is safeguarded from damage due to parallel arc faults by a circuit that provides several levels of protection. A semiconductor switch (18) and a current sensor (24) are placed in series with the electrical equipment (14). When the current to the equipment exceeds a first threshold for a predefined period of time, the semiconductor switch (18) is rendered non-conductive until the circuit is specifically reset. When the current to the equipment exceeds a greater second threshold, a pulsed signal alternately places the semiconductor switch (18) in conductive and non-conductive states so that the average current applied to the equipment (14) is within an acceptable level. The pulses are measured to determine whether a parallel arc fault has occurred. When the measured pulses (74) are within a predetermined range, a parallel arc fault is declared and the semiconductor switch (18) is rendered non-conductive. Should the current exceed an even greater third threshold, the semiconductor switch (18) is immediately rendered non-conductive until the circuit is manually reset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.