Non-volatile semiconductor memory device
US6590809B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 9, 2002 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Jan 9, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When two bits are stored per memory cell and the two bits are written or read, writing or reading operation has to be performed twice. When a memory array is constructed by using a memory cell, by the access of twice, read time or write time twice as long as conventional read or write time is required. It causes deterioration in speed of a system using the memory. To solve the problem, according to the invention, bit arrangement of a conventional memory cell array is changed according to a writing or reading method With the configuration, a plurality of bytes can be simultaneously written or read by a single access. In order to perform reading at higher speed, a sense amplifier requiring no precharging is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.