Method and apparatus for providing a packet buffer random access memory
US6590901B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 1999 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Mar 31, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9021
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention generally provides a memory device that is optimized for network packet switching. Multiple access ports permit multiple devices to concurrently access the memory in a non-blocking manner. The memory performs all management of network data queues so that all port requests can be satisfied within the real-time constraints of network packet switching. The memory system is expandable, with packet data being distributed across all memories in the system to prevent overloading of any one memory device. Further, the memory system includes input and output queue management functions using pointers that allow input data to be placed on output data queues without the data actually being copied into a new output queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.