Method and system for run-time logic verification of operations in digital systems
US6590929B1 · kind B1 · utility
45Cited by
18References
29Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 8, 1999 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Jun 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318566
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system for controllable run-time verification of operations in a logic structure of a digital system. The system comprises a controllable bit stream generator which produces a controlled bit stream output. The controlled bit stream output corresponds to a bit sequence which instantiates a verification of operations within the logic structure. The system also comprises means for coupling the controlled bit stream output to the logic structure to verify the operations of the logic structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.