Running-sum adder networks determined by recursive construction of multi-stage networks
US6591285B1 · kind B1 · utility
3Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Nov 20, 2000 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Feb 21, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A technique for physically implementing a running sum adder network and configuring the concomitant adder network of elements. A 2k+1×2k+1 adder network has the size 2k+2−k−3 and depth 2k+1; thus the adder network achieves a very good balance between the measures of size. The adder network utilizes a systematic design method based upon a recursive construction algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.