Pipelined carry-lookahead generation for a fast incrementer
US6591286B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 18, 2002 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Jan 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An incrementer pipelines the generation of carry lookahead signals. Count registers hold a current count of the incrementer. The current count is fed back as inputs to sum logic, which generates sum bits that are latched into the count registers as a next count. All-ones detect logic detects when all lesser-significance bits in the current count are ones. When all lesser bits are ones, the sum logic toggles the count bit to generate the sum bit for that bit position. Pre-carry logic generates pre-carry lookahead signals from the sum bits. The pre-carry lookahead signals are latched into pipelined carry registers. The pipelined carry registers drive pipelined carry lookahead signals to the all-ones detect logic. Thus carry lookahead signals are generated from a prior sum but used in a next clock cycle to generate then next sum.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.