Memory controller with arbitration among several strobe requests
US6591323B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 13, 2002 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Aug 13, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1647
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controller for a memory partitioned into a plurality of banks and divided into addresses that are accessed by a plurality of row access strobe signals and a plurality of column access strobe signals. The controller generally comprising a queue state machine, a plurality of transaction state machines and an arbitor. The queue snare machine may be configured to allocate a plurality of memory commands received by the controller among a plurality transaction state machines. A first of the transaction state machines may be configured to issue a first strobe request to assert one among the row access strobe signals and the column access strobe signals in response to receiving a first of the memory commands. A second of the transaction state machines may be configured to issue a second strobe request to assert one among the row access strobe signals and the column access strobe signals in response to receiving a second of the memory commands. The arbitor may be configured to arbitrate between the first strobe request and the second strobe request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.