Debug controller in a data processor and method therefor
US6591378B1 · kind B1 · utility
24Cited by
12References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2000 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Feb 22, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for debug control in a pipelined data processor where an offset is determined for the program counter (PC) based on the state of the pipeline. The offset is subtracted from the PC value at the end of a debug session. The resultant PC value restarts fetching of a last unsuccessfully completed instruction. If the offset indicates a change to the PC value, the instruction register is adjusted to a nop to allow the pipeline to restart execution after the last successfully completed instruction. In one embodiment, the state of the machine is preserved prior to exception handling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.