Technique for facilitating circuitry design
US6591399B1 · kind B1 · utility
21Cited by
4References
36Claims
0Family size
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Key dates
| Filing date | Dec 28, 2000 |
| Grant date | Jul 8, 2003 |
| Priority date | — |
| Expiry date | Jun 13, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for facilitating circuitry design by providing minimum technology to minimize power consumption is disclosed. In one embodiment, the technique is realized by providing a system comprising estimation tools including power/density estimation tools, subsystem performance estimation tools, and performance analysis tools. Based on components and goals input by the user the system provides comparisons to facilitate minimum power consumption, maximum density, and maximum throughput. The user proceeds from a component level to a system level to arrive at an optimal system design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.