Acquistion timing loop for read channel
US6594098B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 12, 2000 |
| Grant date | Jul 15, 2003 |
| Priority date | — |
| Expiry date | Jun 18, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B5/09
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A signal from a storage medium is processed in a data channel to form digital data. An amplifier and a sampler convert the storage medium signal into a timed sample sequence. A first equalizer and adjuster operates to equalize the timed sample sequence and to adjust the gain of the amplifier and timing of the sampler in a preamble segment of the signal. A second equalizer and adjuster circuit to equalize the timed sample sequence for detection and to adjust the gain of the amplifier and the timing of the sampler operates in a user data segment of the signal. An FIR equalizing filter in the second equalizer and adjuster circuit is controlled by a set of parameters to accurately equalize a large range of waveforms in the user data segment of the signal and an FIR equalizing filter in the first equalizer and adjuster circuit is controlled by a smaller set of related set of parameters adapted to accommodate rapid adjustment during synchronization in the preamble segment of the signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.