Method for optimizing distribution profile of cell threshold voltages in NAND-type flash memory device
US6594178B2 · kind B2 · utility
25Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 31, 2001 |
| Grant date | Jul 15, 2003 |
| Priority date | — |
| Expiry date | May 31, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is operable in a non-volatile memory device of a type having a plurality of blocks formed of a plurality of memory strings in which a plurality of memory cells are connected in series in which a programming operation is conducted after erasing memory cells. The method essentially including the steps of: erasing data held in the memory cells in a unit of the block; and applying a soft program voltage to word lines coupled with the erased memory cells in the unit of the block. The method improves a threshold voltage profile after an erasing cycle, whereby program stress can be minimized in a follow-up program operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.