High availability computing system
US6594735B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1998 |
| Grant date | Jul 15, 2003 |
| Priority date | — |
| Expiry date | Dec 28, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2041
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high availability computing system having multiple processing elements capable of simultaneous execution of multiple software programs and seamless software upgrades is disclosed. The system comprises multiple processing elements, each processing element capable of accessing memory at processing element memory addresses; and multiple memory modules each having a plurality of alterable memory units, each memory unit identified by a system memory address within a defined address space. The system further includes a memory element interface in communication with each of the memory elements permitting alteration of the defined address space for the memory element. An address mapper is interconnected between each of the processing elements and at least one of the memory elements. The address mapper is capable of mapping a processing element memory address to a global memory address within a defined address space. Thus, the system may allocate memory addresses used by a single one of the memory elements to an address space used by only a single processing element. The system further has access ports to each of the memory elements, thus allowing the single processing element limited acc…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.