System for preventing power save mode during a pre-set condition while tracking patterns of use in order to modify the pre-set condition to accommodate the patterns of use
US6594767B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2000 |
| Grant date | Jul 15, 2003 |
| Priority date | — |
| Expiry date | Mar 31, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer peripheral device is prevented from being in power save mode by either forcing the peripheral device out of power save mode or preventing the peripheral device from entering power save mode. A timing mechanism tracks time. The timing mechanism either tracks the time of day, the day of the week, an elapsed time, or a combination of these times. The time tracked by the timing mechanism is compared to a pre-set condition stored in a storage device. If the time meets the pre-set condition, the computer peripheral device is prevented from being in power save mode. The computer peripheral device is prevented from being in power save mode by either transmitting a job to the peripheral device for processing, accessing the control means of the peripheral device and terminating the power save mode, or temporarily disabling the power save mode for the peripheral device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.