Simultaneous processing for error detection and P-parity and Q-parity ECC encoding
US6594796B1 · kind B1 · utility
63Cited by
5References
16Claims
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Key dates
| Filing date | Jun 30, 2000 |
| Grant date | Jul 15, 2003 |
| Priority date | — |
| Expiry date | Jun 16, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1515
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Method and system for receiving each data element of an array once and simultaneously forming an EDC error detection term, two ECC P-parity checkbytes and two ECC-Q-parity checkbytes for the array. Each data element is read once from memory and is received by an EDC processor, by an ECC-P processor and by an ECC-Q processor and is processed in parallel and substantially simultaneously by the three processors to form an EDC error detection term and the ECC-P-parity and ECC-Q-parity checkbytes, using shift registers with feed-back and/or weighted summation of selected register contents.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.