System and method for performing timing analysis, including error diagnosis, signal tracking and clock skew
US6594806B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 7, 2000 |
| Grant date | Jul 15, 2003 |
| Priority date | — |
| Expiry date | Nov 10, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for performing timing analysis comprising inputting circuit timing information for a circuit, including temporal constraints between events of a desired circuit operation. A timing diagram representing the desired circuit operation, based on the circuit timing information is generater. All violated constraints within said timing diagram are identified. The method forces no violations of said violated constraints by designating the violated constraints as Non-Breakable (NB) constraints, such that a time difference from a source event to a destination event which defines said NB constraint is no less than a minimum bound and no more than a maximum bound of a linear constraint representing a timing requirement between the source and the destination events.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.