Reconfigurable integrated circuit with a scalable architecture
US6594810B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2001 |
| Grant date | Jul 15, 2003 |
| Priority date | — |
| Expiry date | Oct 4, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2213/13322
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) includes a number of function blocks (FB), of which at least one is re-configurable. Each of the FBs may be a reconfigurable function or a non-reconfigurable function or recursively expanded with additional “nested” function blocks. The IC further includes a number of input pins, a number of output pins, and a number of crossbar devices. The elements, at least at the IC level, are coupled in a manner such that all input signals are provided to the FBs through a first subset of the crossbar devices, all internal signals are routed from one FB to another FB through a second subset of crossbar devices, and all output signals are routed from the FBs to the output pins through a third subset of crossbar devices. To increase routability and speed each of the crossbar device output has a single fanout. Additionally, each of the crossbar devices may provide only one input to each other crossbar device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.