Method of manufacturing semiconductor device
US6596571B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2001 |
| Grant date | Jul 22, 2003 |
| Priority date | — |
| Expiry date | Jun 5, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6721
Abstract
Conventionally, when a TFT provided with an LDD structure or a TFT provided with a GOLD structure is to be formed, there is a problem in that the manufacturing process becomes complicated, which leads to the increase in the number of steps. An electrode formed of a lamination of a first conductive layer (18b) and a second conductive layer (17c), which have different widths from each other, is formed. After the first conductive layer (18b) is selectively etched to form a first conductive layer (18c), a low concentration impurity region (25a) overlapping the first conductive layer (18c) and a low concentration impurity region (25b) not overlapping the first conductive layer 18c are formed by doping an impurity element at a low concentration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.