Method for manufacturing a semiconductor memory device
US6596645B2 · kind B2 · utility
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6References
2Claims
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Assignee
Inventor
Key dates
| Filing date | Jul 31, 2001 |
| Grant date | Jul 22, 2003 |
| Priority date | — |
| Expiry date | Jul 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for manufacturing a semiconductor memory device, particularly ferroelectric devices, in which an interlayer dielectric (ILD) layer formed on an upper part of a semiconductor substrate containing a capacitor structure is etched under conditions in which the plasma electron temperature is maintained in a range between 2.0 eV and 4.0 eV to open contact holes to expose the capacitor structure and thereby avoid degradation of the device characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.